Deviation indication system employing prescribed and measured values



Oct. 13, 1970 G. KAPS 3,534,336

DEVIATION INDICATION SYSTEM EMPLOYING PRESCRIBED AND MEASURED VALUES Filed April 5, 1967 5 Sheets-Sheet 1 SOURCE OF TIMING SIGNALS 1 A 1 T fP INVERTER 2 Q 1 l1?- AN TICOINCIDENCE ODIFFERENCE C2 1 R ER COUNTER OUTPUTS Av \VR INVENTOR.

GER HARD KA PS i e-we. filidibl AGENT Oct. 13, 1970 G. KAPS 3,534,336

DEVIAIION INDICATION SYSTEM EMPLOYING PRESCRIBED AND MEASURED VALUES Filed April 5, 1967 5 Sheets-Sheet Z FIGZa INVENTOR.

GER HARD KAPS MEN Oct. 13, 1970 P 3,534,336

DEVIATION INDICATION SYSTEM EMPLOYING PRESCRIBED AND MEASURED VALUES Filed April 5, 1967 5 Sheets-Sheet 3 m G n c2 -r R2 ERA ER S FF; C2 8V1 6V2 EVA Ev ""7 EH INVENTOR.

GERHARD KAPS BY Lode. fl-W AGENT Oct. 13, 1970 e. KAPS 3,534,336

DEVIATION INDICATION SYSTEM EMPLOYING PRESCRIBED AND MEASURED VALUES Filed April 5, 1967 5 Sheets-Sheet 4 6K1 L SE As GAT W q En i GAP AP (+)fi 3L At INVENTOR.

GERHARD KAPS 0a. 13, 1970 G. KAPS 4 3,534,336

DEVIATION INDICATION SYSTEM EMPLOYING PRESCRIBED AND MEASURED VALUES Filed April 5, 1967 5 Sheets-Sheet 5 ta T TM 2a= zs-fi mun-E) FEGEa It 1 7 My TM a TM 2pm TM'Z5)(1' INVENTOR.

GERHARD- KAPS BY M KW AGENT limited States US. Cl. 340-168 5 Claims ABSTRACT OF THE DISCLGSURE A digital control circuit for producing time intervals proportional to control deviations between actual and reference control signals provided with an arrangement of reversible counters and associated logic circuits for receiving pulses representing sampling time and preselected difference signals and routing them to sum and diiference counters for producing the desired control difference indication signals.

This invention relates to an improvement in or a modification of the invention described and claimed in copending US. patent application Ser. No. 544,007 filed Apr. 20, 1966. As described therein, a control system uses frequency and time proportional signals and measured quantities are represented by frequency-analogous signals. The prescribed quantities are set and/ or introduced in the form of digits, especially for ratio controls and, for the processing of measured and prescribed quantities, each control circuit includes only one counter and means for controlling it and for producing time intervals proportional to the deviations from the controlled quantities, the signs of these deviations being taken into account.

The operation of this arrangement, shown in FIG. 1, will now be described.

Synchronized pulses at the measured frequency (measured quantity) i, are applied to input H and supplied through a summation device S and an anticoincidence stage A to the forward input E of a difference counter Z. Assuming bistable trigger circuits FF, and FF to be initially in the rest condition shown, and-gates G and G are prepared. When the measured quantity 1, is smaller than its prescribed value f the difference counter Z will not have yet counted to the prescribed value predetermined in a preselection device SE when a synchronized pulse produced by a time base T appears. A clock pulse coincident with the time-base pulse causes the circuit FF 1 to change its condition. Consequently, 1 potential is applied to the output A of the and-gate G Through an and-gate GV2, which is controlled by G and by a trigger circuit FF a pulse sequence of frequency f =f appears at the second input of the summation device S and this device adds this pulse sequence to the measured pulse sequence. As a result the counter Z counts forward according to a frequency f +f When the prescribed value set in SE is reached, this causes FF to change back to the initial rest condition, the gate G to be closed through an inverter stage N and the counter Z to be reset to zero through an and-gate G Then the measured quantity only is introduced and counted in the counter until the appearance of the next time-base pulse again initiates the described process. The time interval 2, proportional to the control deviation is derived from the output A of the gat G With a constant control deviation in the steady state, the state of the counter Z has the variation with time shown in FIG. 2a.

Next, we will consider the case where the measured quantity f, is greater than its prescribed value f,. It is again assumed that the bistable trigger circuit FF and FF initially are in the conditions shown. By introducing the measured frequency 1, into the counter Z, the prescribed value of the counter contents, which value is predetermined in the preselection device SE, is exceeded each time before a time-base pulse appears. Through G the resulting 1 potential set up at the output of SE during the interval between two measured-frequency pulses causes FF to be changed over by the clock pulse and its output C is marked. When the time base pulse is received, the circuit FF, is caused by the clock-pulse to change its condition, so that the gate G is prepared and the and-gate G is opened. Through the and-gate G which is controlled by G and a trigger circuit FF pulses at the pulse sequence frequency f =f are applied to the backward input of the counter Z. As it is assumed that f is greater than i the counter counts backward at a frequency corresponding to the difference f f When the counter has counted down to the prescribed value preset in SE, this results in that through N G and G backward counting is stopped, through G FF is returned to the initial condition, the counter is reset to zero and FF is returned to the initial condition. Then the counter counts forward at the measured frequency 1, until the prescribed value is reached, and the described process is again initiated. The time interval t which is proportional to the control deviation is now derived from the output A of the gate G The variation of the contents of the counter Z with time is shown in principle in FIG. 2b for the steady state with a constant control deviation.

When there is no control deviation, the counter Z reaches the prescribed value preset in SE exactly at the instant at which a time base pulse is received. In this event, the counter is immediately reset to Zero through the and-gate G While FF is prevented from changing condition through N and the and-gate G The circuit FF which is prepared through G is caused to change condition by the clock pulse, but after the zero-setting of the counter it is immediately returned to its initial condition.

In the above described circuit arrangement, however, only prescribed values other than zero can be preset in the preselection device SE. If the prescribed value zero is preset, both preparing inputs of the trigger circuit F1 are given 1 potential as long as the counter Z is at zero and as soon as FF is in the initial condition. The circuit FF is caused to change condition at the clock pulse frequency. The appearance of a measured-frequency pulse, that is to say f f terminates the changing over of FF In this process the output C; may accidentally remain marked, so that owing to the next timebase pulse, the counter does not count backward at the difference frequency f f but forward at the sum frequency f -H to its maximum capacity and thus to zero. This means that statistically an indication is given of a control deviation in the wrong direction and with a wrong value. Moreover, the statistically occurring coincidences of the output pulses of the summation device S with the zero-setting signals for the counter Z give rise to counting errors which result in wrong output signals at the output A It is an object of the present invention to eliminate these limitations. According to the invention, for this purpose, the means for controlling the counter and for producing time intervals proportional to the control deviations, while taking the signs into account, the signs are arranged so that the pulses of a time base which determines the sampling time are directly applied to a preparing input of a bistable trigger circuit. The second preparing input of the trigger is connected to the output of a preselection device, which serves to introduce the prescribed values and is controlled by the output of the difference counter. The outputs of this first bistable trigger circuit, which is connected through two and-gates to the output of the preselection device, controls the preparing inputs of the second bistable trigger circuit, one of the outputs of the first bistable trigger circuit, through a preparing input, directly triggers a third bistable trigger circuit which delivers one half of the clockpulse frequency and opens two further and-gates which are prepared by the outputs of the second bistable trigger circuit and, in common, by the output of a nand-gate, which in turn relates the output signals of the third bistable trigger circuit to the reset-to-zero signal for the difference counter. The outputs of the last-mentioned and-gates control two further and-gates, the inputs of which are connected in common to that output of the third bistable trigger circuit which in the rest condition is marked. The output signals of one and-gate are applied directly and those of the other through a summation device to the inputs of an anticoincidence element preceding the difference counter. In the summation device the output signals of one and-gate are added to the measured-frequency pulses and related to the reset-to-zero signals for the difference counter, these reset-to-Zero signals being produced by the and-gate the input of which is connected to that output of the first bistable trigger circuit which is not marked in the rest-condition and to the output of the preselection device.

In order that the invention may readily be carried out, embodiments thereof will now be described, by way of example, with reference to the accompanying drawings, in which FIG. 1 is the circuit diagram of a control arrangement,

FIG. 2 shows in principle the variation of the counter contents with time in the steady state; (a) when the measured value is smaller than the prescribed value; and (b) when the measured value is greater than the prescribed value,

FIG. 3 is a circuit diagram of a control arrangement according to the invention,

FIG. 4 is a circuit diagram of a modification of the control arrangement according to the invention,

FIGS. 5a and 5b illustrate the variation of the counter contents with time in the steady state for the arrangement shown in FIG. 4, and

FIG. 6 is a circuit diagram of an embodiment of the summation device.

In the circuit arrangement shown in FIG. 3, the pulses at the measured frequency (measured quantity) 7, which are synchronized with the clock-pulse are applied to the input E of a summation device S the output of which is connected to the forward input E of the anticoincidence element A preceding the difference counter Z. It is assumed that the bistable trigger circuits FF and FF and FE; are in the rest condition shown. As a result the and-gates G G and G are prepared and the output of the nand-gate G is at l-potential. When the measured frequency f, is smaller than its prescribed value f on the appearance of a time-base pulse the difference counter Z has not yet reached the prescribed value stored in the preselection device. The change of condition of the trigger circuit FF 1 initiated by the clock pulse coincident with the time-base pulse causes the and-gate G to be opened and l-potential to be set up at the second preparing input of the trigger circuit F1 As a result pulses at the frequency f :f are applied to the stimmation device S through the and-gate 6 The difference counter Z counts forward at the frequency f -l-f until the prescribed value set in the preselection device SE is reached. When the prescribed value is reached, this prepares the return of FF to the initial condition and hence the blocking of the gate G and, through the and-gate G the resetting to zero of the difference counter. When the prescribed value is reached simultaneously with the production of an output signal by F1 the and-gate G is immediately blocked through the nand-gate G so as to prevent this pulse from reaching the counter. However, when the prescribed value is reached simultaneously with the appearance of an output pulse of the summation device S derived from the measured quantity, this pulse has to be stored intermediately, being introduced and counted in the forward direction when the difference counter has been reset to zero. The intermediate storage takes place in the summation device S to which for this purpose the output signals of the gate G are applied through a third input. When the counter Z has been reset to zero, only the pulse sequence at the measured frequency is counted in the forward direction until the next time-base pulse causes a repetition of the described process. Time intervals proportional to the control deviation will be derived from the output A of the gate G and pulse trains proportional to the control deviation from the output Avg of the gate G With a constant control deviation, the contents of the counter Z in the steady state vary with time in the manner shown in principle in FIG. 2a.

When the measured quantity 1, is greater than its prescribed value f the counter reaches the prescribed value preset in SE each time before the appearance of a timebase pulse. Starting from the initial position of the bistable trigger circuit which is shown in the figure, this reaching of the prescribed value causes the trigger circuit FF to change its condition through the and-gate G Thus, it is no longer the gate G but the gate G which is prepared. The time-base pulse again causes the trigger circuit PF to change its condition, l-potential being set up at the output 6 As a result, the gate G is opened and FF is prepared for a change in condition at clook-pulse frequency. Now the pulses of frequency f =f are applied through G to the backward input of the counter Z, so that it counts backward at a frequency corresponding to the difference f -f When the prescribed counter reading preset in SE is reached again, this prepares the return of FF and, through the Gate G the return of P1 and the resetting to zero of the counter Z by the clock-pulse. Subsequently, the counter counts forward at the measured frequency 1, until the prescribed value is reached and the described process is repeated. Time intervals and pulse trains proportional to the control deviation are produced at the outputs A and A respectively. With a constant control deviation, the contents of the difference counter Z in the steady state vary with time in the manner shown in principle in FIG. 2b.

When the counter reaches the prescribed value simultaneously with the appearance of a time-base pulse or when the time-base pulse appears after the counter has reached the prescribed value but before the appearance of a further pulse at the measured frequency f no output signal is produced. In the first case, the trigger circuit FF which is prepared by the time-base pulse, and the trigger circuit FF which is prepared through G by the counter reaching the prescribed value and byifi are simultaneously caused to change condition. Then the resetting to zero of the counter Z and the return of the trigger circuit FF are prepared through G and the return of the trigger circuit FF is directly prepared by the counter reaching the prescribed value. The gate G is not opened because the output of G is at 0 potential. Simultaneously with the resetting to zero of the counter Z, the trigger circuits FF and FF are reset to their initial condition, the trigger circuit FP is caused to change condition and returns to the initial condition on the appearance of the next clock-pulse. In the second case, the trigger circuit FF is caused to change condition, as is F1 but the latter only after the application of the time-base pulse. Then the trigger circuits are reset to the rest condition and the counter Z is reset to zero,

in the same manner as described with reference to the first case.

If the prescribed value zero is preset in the preselection device SE, only positive control deviations can occur since negative frequencies cannot exist physically. Starting from the initial condition of the trigger circuits, which is shown, and with the counter being at Zero, the trigger circuit FF is prepared through G and caused to change condition. If no measured-frequency pulse is received before the appearance of the time-base pulse, the trigger circuits are caused to change condition in a manner similar to that of the above described case in which the timebase pulse appears after the prescribed value has been reached and before a further pulse at the measured fre quency is received. If there is a deviation however, the trigger circuit FF is caused to change condition, ie to leave the rest condition, and hence G is opened, after which the counter counts backwards at the difference frequency f f until it reaches the prescribed value zero. Then the trigger circuits FF and FF are reset to the rest condition. Since the counter still is at the prescribed value, the next clock pulse immediately causes PR to leave the rest condition, so that after the next time-base pulse, when pulses of measured frequency are counted, the counter again counts backwards at the difference frequency f f A drawback of the control system shown in FIG. 3 is that in order to allow for a positive deviation of, for example, 100% the counting capacity of the difference counter Z must be twice the maximum prescribed value Z max, and that it is not the counter contents reached at the sampling instants but their respective differences from the preset prescribed value which is approximately proportional to the deviations.

FIG. 4 shows an embodiment of a control system according to a further development of the invention, which obviates these drawbacks and is designed for synchronous operation. The pulses at the measured freqeuncy (measured quantity) which are synchronized with the clock pulse are applied to the input E with the bistable trigger circuits FF FF 0 and FF in the rest-condition, as shown, the pulses pass through the and-gate G and the summation device S to reach the backward input E of the anticoincidence element A preceding the difference counter Z. The counter counts backward from the preset prescribed value to zero. When the measured frequency f is smaller than its prescribed value the difference counter Z has not yet reached zero when a synchronized sampling pulse produced by the time base T is received. The clock-pulse which is coincident with the sampling pulse cause the circuit FF to change its condition, so that the bistable trigger circuit =FF is triggered from the output C and the andgate C which has been prepared through the inverter stage N, is opened. Through the and-gate G pulses at the frequency f =f reach the output A and are applied to the summation device S. The difference counter continues counting at a frequency corresponding to the sum f +f When the counter reaches zero, this is detected in the gate G and causes through the inverter stage N the gates G and G to be blocked and the trigger circuit FF to be returned to the initial condition, and through the and-gate G and the preselection device SE the counter to be set by the clock pulse to the prescribed value Z preset in SE. If the counter reaches zero at the same time as the appearance of an output pulse of the summation device S produced by the measured frequency f,, this pulse must be intermediately stored and introduced into the difference counter to be counted backwards after the counter has been preset. The intermediate storage is effected in the summation device S, to which the output signals of the gate G are applied through a control input. After the difference counter Z has been preset, the pulses of measured frequency i, only are counted backward, until on the appearance of the next sampling pulse the described cycle is repeated. With a constant control deviation the contents of the difference counter Z in the steady state vary with time in the manner shown in principle in FIG. 50.

We will next consider the case that the measured quantity f is greater than its prescribed value f Again the bistable trigger circuits are assumed to be in the rest condition shown and the difference counter Z to be at the preset value Z When, now, the pulses of the measured frequency f are introduced into the counter through Efi, m, S and A and counted, the counter reaches zero before a sampling pulse is received. Through the gates G and G the change in condition of the trigger circuit FF by the clock pulse is prepared. Subsequently the gate G is in the closed condition and the gate G is open so that the pulses at the measured freqeuncy are applied to the forward input E of the anticoincidence element A. The difference counter Z continues counting forward. The reception of a sampling pulse produced by the time base T results in the circuit FF to be reversed by the clockpulse, so that the trigger circuit FF is triggered and the and-gate G which has been prepared by the inverter stage N, is opened. Subsequently pulse signals at the frequency f =f produced by F-F are applied through the gate G to the output A and through the summation device S and the anticoincidence element A to the backward input E of the difference counter Z. Since f is greater than i the difference counter Z counts backward according to the frequency f f When the counter reaches zero, this is detected in the gate G This gate blocks the gates G and G through the inverter stage N and causes FF and, through the gate G FF to return to the initial condition and, through G and the preselection device SE, cause the counter Z to be set to the prescribed value Z by the clock pulse. Subsequently the pulses at the measured frequency f alone are counted backward, and when the counter reaches zero the described cycle is repeated. With a constant control deviation the counter contents vary with time in the manner shown in FIG. 5 b in the steady state.

If the counter reaches zero simultaneously with the appearance of a pulse at the measured frequency f this pulse must be prevented from being directly applied to the difference counter Z and therefore must be intermediately stored to be introduced into the difference counter Z and counted backward after the counter has been preset. For this purpose the and-gate G detects the coincidences of the output signals of the gates G and G The output signals of G are applied to the blocking input E of the anticoincidence stage A to block the counter inputs and to the summation device S to be intermediately stored.

Time intervals which are proportional to the respective amounts of the control deviations in the steady state, are available at the output A of the gate G as are pulse trains at the output A of the gate G In addition, as FIG. 5 shows, in the steady state the value Z reached by the difference counter Z at the respective sampling instant is approximately proportional to the amount of the control deviation:

Z11: (f1 s) fi fo) This approximation is the better, the greater f is chosen. The signs of the output signals are determined by the condition of the trigger circuit FF 1 potential at the output 6 means the control deviation is positive and 1 at the output C means: the control deviation is negative.

When the sampling pulse produced by the time base appears simultaneously with the counter reaching zero owing to a pulse at the measured frequency f or subsequent thereto but prior to the appearance of a further measuredfrequency pulse, no output signal is delivered. In this case, the trigger circuits FF and FF which are in the rest condition and are prepared through G and G and by the sampling pulse, respectively, are simultaneously or consecutively reversed. Since the reading of the difference counter remains unchanged, the trigger circiuts FP which has been prepared through G and G and FF which has been prepared through G are simultaneously returned to the initial condition by the clock pulse, the difference counter Z, which has been prepared through G G and SE, being preset to the prescribed value Z The 1 potential which in the meantime is set up at the output C of the trigger circuit FF does not cause the production of output signals at the outputs A, and A since the gate G is simultaneously blocked through the inverter stage N.

When the prescribed value zero is preset in the preselection device 5B, the initial conditions of the bistable trigger circuits are different, the difference from the initial conditions shown in the figure being that the output 6 of the trigger circuit FF is marked in the initial condition. Hence, the pulses at the measured frequency f,, which in this event always mean a positive control deviation, are applied through the gate G to the forward input E of the anticoincidence element A preceding the ditference counter. The change in condition of the trigger circuit is effected after reception of the sampling pulses produced by the time base T, as has been described hereinbefore for the case of a positive control deviation.

The operation of the summation device S will now be described With reference to the circuit diagram shown in FIG. 6. The summation device comprises a bistable trigger circuit FF and the nor elements N N and N The pulses at the measured frequency f, are applied to the input E the pulses at the frequency f =f to the input E and the zero-setting pulses for the counter Z to the input E The bistable trigger circuit FF, which initially is in the rest condition, is caused to change this condition by each clock pulse which coincides with the pulse applied to the input E When no coincident pulse appears at E and/or E the trigger circuit FF is returned to the rest condition by the next clock pulse, so that the input pulse appears at the output C of the trigger circuit and, through N and N at the output A with a delay of one pulse period. For the output C and the input E the two nor elements N and N constitute an or-function, that is to say, the sum of the pulses at C and B appears at the output A when these pulses do not coincide. When an output pulse at C coincides with an input pulse at E the trigger circuit FF is prevented through N from being returned to the rest condition by the clock pulse following the pulse at E and it can only be returned to the rest condition by the clock pulse following the pulse at E At the outputs C and A a pulse of twice the clock pulse period is produced, which is counted as two discrete pulses by the associated synchronous counter.

Through N input pulses at E which coincide with output pulses at C act upon the trigger circuit FF in the same manner as the pulses at E however, through N they erase the coincident portion of the double pulse produced at C. In this case, the pulse associated with the input pulse at Efi appears at the output A after the zerosetting pulse for the counter Z controlled by A is aptO EGA.

What is claimed is:

1. A control system using frequency and time proportional signals wherein measured quantities are represented by frequency-analogous signals and the prescribed quantities are preset and/or introduced in the form of digits for the processing of measured and described quantities for producing time intervals proportional to control deviations between measured and prescribed quantities in accordance with sampling intervals, comprising a time base pulse source for determining the sampling time and providing a series of pulses directly applied to one preparing input of a first bistable trigger circuit having first and second preparing inputs, the second preparing input of said first flip-flop being connected to the output of a preselection device, said preselection device containing the prescribed values and controlled by the output of a difference counter, means coupling the outputs of said first bistable trigger circuit to an input of each of a first and second AND gate, said AND gates further receiving an input from the output of said preselection device, means coupling the outputs of each of said AND gates to respective inputs of a second bistable trigger circuit having complemental outputs, means connecting one of said first trigger circuit outputs to a preparing input of a third bistable trigger circuit thereby producing from said third trigger circuit a frequency one-half of the clock pulse frequency, and to an input of each of a third and fourth AND gate, said third and fourth gates each responsive to the respective outputs of the second bistable trigger circuit, a reset to zero line coupled to said counter, a NAND gate coupling the output signals of said third bistable trigger circiut and the reset-to-Zero signal from said reset to zero line, to a further input of said third and fourth AND gates the outputs of said latter AND gates coupled to the respective inputs of fifth and sixth AND gates, the inputs of which are together connected to the output of said third bistable trigger circuit, said latter output marked in the rest condition, means applying the output signals of said fifth AND gate directly to a first input of an anticoincidence element, means coupling the output of said sixth AND gate to a summation device, said summation summing said sixth AND gate output and said measured frequency, and responsive to a reset to zero signal from said reset to zero line for producing a summation output, said summation output coupled to a second input of said anticoincidence device, said first input of said anticoincidence device coupling a forward counting input to said counter, said second input of said anticoincidence device coupling a backward counting input to said counter, said reset-to-zero signals being supplied by said first AND gate the input of which is connected to said first output of said first bistable trigger circuit and to the output of said preselection device.

2. The combination of claim 1, said summation device comprising a fourth synchronous trigger having a first input receiving said measured quantity rate signal, a second input coupled to the output of a first NOR gate, said NOR gate having a first input responsive to said third trigger means output signal and a second input responsive to said reset signal, a second NOR gate having a first input responsive to said second means output signal and a second input responsive to the output of said fourth trigger circuit, and a third NOR gate having a first input coupled to the output of said second NOR gate and a second input responsive to said reset signal and an output, said latter output being coupled to said counter.

3. A control system for providing an indication of control deviation between a prescribed and measured quantity comprising a counter, said counter set to said prescribed value, means coupling said measured value to said counter, said counter thereafter counting backwards from said prescribed value towards zero at a first rate, second means responsive to a sampling signal for causing said counter to count toward zero at a second rate, third means responsive to a zero count in said counter for blocking said second means and for resetting said prescribed value in said counter, the duration between said sampling signal and said zero counter state representing said control deviation.

4. A synchronous system operative under a predetermined clock pulse rate for providing an indication of control deviation between a prescribed and a measured quantity rate signal comprising a counter, a selection circuit for setting said counter to said prescribed quantity, first means applying said measured quantity to said counter whereby said counter counts toward zero at said measured quantity rate, a first synchronously operative trigger circuit responsive to a sampling pulse for changing from an initial condition to a complementary condition, a second synchronously operative trigger circuit coupled to said first trigger circuit and responsive to said change of condition for providing an output signal at one-half the synchronous clock pulse rate, second means coupling said second trigger circuit output to said first means whereby said counter continues to count toward zero at a modified rate determined by the sum of said second trigger circuit output signal rate and said measured quantity rate, third means coupled to said counter and responsive to a zero condition therein for providing an output signal, said third means output being connected to an input of said first trigger circuit, fourth means coupling the output of said third means to said second means, said fourth means responsive to said third means output signal for blocking passage by said second means of said second trigger circuit output signal to said first means, fifth means coupled to the output of said first trigger circuit, said fifth means responsive to said first trigger circuit initial condition and to said third means output signal for providing a first output condition, said fifth means responsive to said first trigger circuit complemental output and to said third means output signal for providing a second output condition, said fifth means output coupled to the input of said first means, said first means responsive to said first output condition for causing said counter to count forward from zero at said measured quantity rate, said first means further responsive to said second output condition for coupling both said second trigger circuit output and said measured quantity rate to said counter whereby said counter counts toward zero at a modified rate determined by the difierence between said second trigger circuit output signal rate and said measured quantity rate, said fifth means responsive to said third means output and the complemental output of said first trigger for providing a reset signal, said selection circuit responsive to said reset signal for resetting said counter to said prescribed quantity, said first trigger circuit responsive to said third means output signal for changing from said complementary condition to said initial condition, and said first means further responsive to the simultaneous occurrence of a further measured signal and said reset signal for blocking the input to said counter and to store said further measured signal until the termination of said reset signal whereby said further measured signal is then counted in said counter, the duration between said sampling pulse and said zero count providing said control deviation.

5. A control system as claimed in claim 4- wherein said first means includes a summation device for producing said modified rate, said summation device comprising a third synchronous trigger having a first input receiving said measured quantity rate signal, a second input coupled to the output of a first NOR gate, said NOR gate having a first input responsive to said second means output signal and a second input responsive to said reset signal, a second NOR gate having a first input responsive to said second means output signal and a second input responsive to the output of said third trigger circuit, and a third NOR gate having a first input coupled to the output of said second NOR gate and a second input responsive to said reset signal and an output, said latter output being coupled to said counter.

References Cited UNITED STATES PATENTS 3,391,275 7/1968 Bullock et al 23515l.1 3,427,442 2/1969 Sklaroff 235151.1

THOMAS A. ROBINSON, Primary Examiner US. Cl. X.R. 

